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High density and through wafer copper interconnections and solder bumps for MEMS wafer-level packaging

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Abstract

This paper proposes an innovative process combining the electroforming of high-density and through-wafer copper interconnections and solder bumps for advanced MEMS packaging. Vias with the diameter of 30 to 100 μm were etched through on a 4-inch and 550 μm-thick silicon substrate by ICP-DRIE process for an aspect ratio up to 18.3. MRTV1 silicon rubber layer was employed for substrates quickly releasing after copper-interconnections electroforming. Compared to the tedious wet etching or mechanical polishing process, this peel-off relasing process provides a simpler way. After another lithography process, mushroom shape eutecic solder bumps (63Sn/37Pb) were directly electroformed on the top of each copper interconnection with the height of 100 μm, and reflowed at 200 °C for 5 min to form solder spheres. The feasibility of making highly dense and uniform electrical interconncetions has been successfully demonstrated on the wafer with fabricated micro temperature sensors. The estimated resistance for the copper-column of different diameters are characterized lower than 13.1 mΩ and this process provides a bump density up to 9648 interconnects/cm2.

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Correspondence to C.-J. Lin.

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This paper was partially supported by the contract NSC 89–2323-B-007–005, through National Science Council, Taiwan. We also appreciate the help from MicroSystem Common Laboratory at Industrial Technology Research Institute for ICP-DRIE process.

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Lin, CJ., Lin, MT., Wu, SP. et al. High density and through wafer copper interconnections and solder bumps for MEMS wafer-level packaging. Microsystem Technologies 10, 517–521 (2004). https://doi.org/10.1007/s00542-004-0384-5

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  • DOI: https://doi.org/10.1007/s00542-004-0384-5

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