The electrical and physical analysis of Pt gate/Al₂O₃/p-Si (100) with dual high-k gate oxide thickness for deep submicron complementary metal-oxide-semiconductor device with low power and high reliability

Abstract

In order to examine the electrical and physical properties of Al₂O₃ layers with dual thickness on a chip, Pt gate/Al₂O₃ with dual thickness/p-type Si (100) samples were fabricated using atomic-layer deposition, separation photolithography, and 100:1 HF wet etching to remove the first Al₂O₃ layer. Dual metal-oxide-semiconductor (MOS) capacitors with thin (physical thickness, ∼4.5 nm, equivalent oxide thicknesses (EOT): 2.8 nm) and thick (physical thickness, ∼8.2 nm, EOT: 4.3 nm) Al₂O₃ layers showed a good leakage current density of −5.4×10⁻⁶ A/cm² and −2.5×10⁻⁹ A/cm² at −1 V, respectively; good reliability characteristics as a result of the good surface roughness; low capacitance versus voltage measurements (C-V) hysteresis; and a good interface state density (∼7×10¹⁰ cm⁻²eV⁻¹ near the midgap) as a result of pre-rapid thermal annealing (pre-RTA) after depositing the Al₂O₃ layer compared with the single MOS capacitors without the pre-RTA. These results suggest that dual Al₂O₃ layers using the dual gate oxide (DGOX) process can be used for the simultaneous integration of the low power transistors with a thin Al₂O₃ layer and high reliability regions with a thick Al₂O₃ layer.