High interfacial conductivity at amorphous silicon/crystalline silicon heterojunctions

https://doi.org/10.1016/j.jnoncrysol.2007.09.087Get rights and content

Abstract

We performed static coplanar conductance measurements as a function of temperature on samples consisting of n-type hydrogenated amorphous silicon (a-Si:H) deposited onto either glass or p-type crystalline silicon (c-Si). The conductance is found orders of magnitude higher and its activation energy is one order of magnitude lower when the a-Si:H film is deposited on c-Si. It is demonstrated both experimentally and with the help of numerical modeling that this high conductance is due to an electron-rich inversion layer in c-Si at the heterointerface. When a thin (3 nm) undoped silicon layer deposited under conditions that normally lead to polymorphous silicon is inserted at the interface, the coplanar conductance slightly increases, which is attributed to a small increase of the conduction band discontinuity at the interface.

Introduction

The combination with crystalline silicon is one of the most promising fields of development for silicon thin films (either amorphous, polymorphous or microcrystalline) that are deposited at low temperature (T < 250 °C) by plasma enhanced chemical vapor deposition techniques. Indeed, the low deposition temperature ensures a full compatibility with the already processed components and circuits in the crystalline silicon wafer (in particular no diffusion of species will alter the properties) and opens various potential applications, such as above integrated circuits detectors and heterojunction solar cells [1]. Although many efforts have been made in the past few years to improve the interface quality between hydrogenated amorphous silicon (a-Si:H) and crystalline silicon (c-Si), leading to conversion efficiencies of silicon heterojunction solar cells above 21% [2], the detailed description of the a-Si:H/c-Si interface still needs to be improved. We here focus on the interface between n-type a-Si:H and p-type c-Si. We measured the coplanar conductance of devices having various a-Si:H layer thickness, without or with an additional interfacial layer deposited under conditions that normally lead to undoped polymorphous silicon (pm-Si:H) on glass [3], [4]. With the help of a numerical model, we show that these simple conductance measurements can give strong indications on the band diagram at the heterointerface.

Section snippets

Samples and experiments

A first series of phosphorus doped a-Si:H films with various thicknesses (20 nm, 100 nm, 200 nm) was deposited by rf PECVD (13.56 MHz) from a silane–phosphine mixture under following conditions: pressure of 50 mTorr, power of 1 W, substrate temperature of 200 °C. For each run, the deposition was done simultaneously onto three different substrates: glass (Corning 1737), Czochralski c-Si wafers (〈1 0 0〉 oriented, p-type, ρ = 14–22 Ω cm), and Float Zone c-Si wafers (〈1 0 0〉 oriented, p-type, ρ = 1–5 Ω cm). Before

Results

The main parameters deduced from the dark current measurements are listed in Table 1. The conductance of the c-Si samples is much higher than that of the glass ones. This is true for all the deposition conditions (with or without undoped polymorphous layer), and it is independent of the a-Si:H layer thickness. Also, the values of the activation energy of the conductance are very different between the two types of samples. While values around 0.2 eV typical for n-type a-Si:H are found for the

Discussion

A simplified equivalent electrical circuit for the dc current transport in our c-Si samples is shown in Fig. 2. One can distinguish three paths between the two top electrodes: (i) the direct path across the n+ a-Si:H layer represented by the conductance Ga-Si:H; (ii) the path across the bulk c-Si represented by the conductance Gc-Si; and (iii) a possible path along the interface, represented by Gint, that will be discussed further below. The path across the a-Si:H layer is the only possible one

Conclusion

Coplanar transport measurements performed on (n) a-Si:H/(p) c-Si heterostructures reveal a high interfacial conductance, which is several orders of magnitude larger than that of the same a-Si:H layer deposited onto glass. This high conductance has been attributed to an electron inversion layer in c-Si at the interface, that is induced by the conduction band mismatch ΔEC between a-Si:H and c-Si. Numerical calculations show that ΔEC must be greater than 0.1 eV to account for the observed effect.

Acknowledgments

This work was partly supported by ANR in the framework of the French National Photovoltaic ‘PHARE’ Project. J. Damon-Lacoste and R. Chouffot thank ADEME and CNRS for their grant.

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    Also, the values of the activation energy of the conductance are very different between the two types of samples. While typical values around 0.18 ± 0.02 eV for n-type a-Si:H are found for the a-Si:H/glass samples, much lower values around 0.019 ± 0.002 eV are obtained for the a-Si:H/c-Si heterojunction samples, which demonstrates the existence of the strong inversion layer at the heterojunction interface [20–22]. Determined from the improved C–V measurements (Eqs. (1) and (3)), the value of ΔEC = 0.17 ± 0.04 eV is found for the conduction band offset between a-Si:H and c-Si.

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    The high carrier concentration in the inversion layer should cause high conductance, if the current–voltage (I–V) characteristics are measured at parallel electrodes on the a-Si:H(n) layer. This was in fact demonstrated by Kleider et al. [14] who measured the parallel conductance (G) on a-Si:H(n) deposited on the p-type silicon substrate higher by orders of magnitude compared to a-Si:H(n) deposited on glass. While G depends on the carrier inversion, which reflects conditions at the heterojunction, coplanar I–V measurements were successfully used for characterization of SHJ structures to determine the band alignment [12] and band bending in the silicon substrate [15].

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    We detailed the calculation and analysis on an (n) a-Si:H/ (p) c-Si heterojunction; similar studies on the reverse structure have been presented elsewhere [7,15] with the planar conductance being related to the hole sheet density Ps. In the past, we already extracted conduction band offsets from planar conductance measurements on samples consisting of around 20 nm of a-Si:H deposited by Plasma Enhanced Chemical Vapor Deposition (PECVD) on a c-Si wafer [5]. However the full dependence of all material parameters was not incorporated into the model, and the band offset was the only parameter used for fitting.

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    The set-up also allows the measurement of the absolute emitted spectral photon flux density for the determination of the quasi-Fermi level splitting [11]. Conductance measurements were performed on samples consisting of (n) a-Si:H layers fitted with top coplanar Al electrodes [12]. These layers were deposited in the same run on three types of substrates: glass (Corning 1737), Czochralski c-Si wafers (<100> oriented, p-type, ρ = 14–22 Ω cm), and Float Zone c-Si wafers (<100> oriented, p-type, ρ = 1–5 Ω cm).

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