Silicon single-electron transistor fabricated by anisotropic etch and oxidation
Introduction
Silicon single-electron transistor (SET) has been largely investigated not only as the potential successor of the MOS transistor for ultralarge scale integrated circuits but also for single-electron logic applications in quantum computing. The SET fabrication processes on silicon are typically developed on SOI wafers by applying high resolution lithographic techniques and anisotropic etchings. Most of them are based on e-beam lithography and reactive ion etching (RIE) [1], [2], [3], [4] even if some other alternative lithographic techniques, such as advanced optical lithography [5] and scanning probe lithography (SPL) [6] have been proposed. As far as the silicon etching is concerned, good results have also been obtained with wet anisotropic etchings such as KOH [6] and TMAH [7].
In this work we propose a silicon SET fabrication process based on a KOH etch applied to structures defined by high resolution e-beam lithography. Selectivity of KOH solutions towards {1 1 1} planes [8] is exploited to define the final shape of the device. Compared to dry etchings, KOH solutions result more simple and cheap and allow to obtain structure with a trapezoidal/triangular cross-section which can be an advantage when a further dimension reduction is necessary, as explained in the following section. The proposed technique can be considered as an evolution of the process used previously to fabricate silicon nanowires with a triangular cross-section [9].
Section snippets
Device description
Fig. 1 reports a perspective view of the device fabricated on a 〈1 0 0〉 SOI substrate by patterning the silicon top layer with e-beam lithography and anisotropic etching. The structure is laterally limited by {1 1 1} planes due to both the selectivity of the KOH solutions towards these planes [8] and a careful alignment of the mask side along the 〈110〉 direction. The device is formed by a small central truncated pyramid connected to the two lateral leads by silicon channels with triangular
Fabrication process
The fabrication process starts from a SOI-SIMOX wafer, 〈1 0 0〉 oriented p doped (1015 cm−3), with a 190 nm top silicon layer, insulated from the silicon substrate by a buried silicon dioxide layer of 380 nm. Dies of 10 × 10 mm2 have been cut and their borders have been used for mask alignment. The top silicon layer is thinned growing 80 nm of SiO2 by means of thermal dry oxidation and removing it by buffered hydrofluoric acid (BHF) etch. An 80 nm SiO2 layer is then regrown for being used as a mask for
Preliminary electrical characterization
The sample has been fixed on a standard TO5 package by means of silver colloidal paste, for providing a contact on the silicon substrate (acting as a backgate) through the metal case. A preliminary electrical characterization has been performed by using an HP4145B parameter analyzer.
Fig. 5 shows IDS–VDS characteristics of the device, measured at room temperature for three different values of the backgate voltage. The curves show interesting step-like effect in the current, probably due to
Conclusions
A process for fabricating a single-electron transistor structure on silicon has been presented. A pyramid isle connected to leads by means of small channels with triangular cross-section is obtained by e-beam lithography and KOH etch. Channel dimensions have reliably been reduced by thermal oxidation. A careful control of the KOH etch parameters (i.e., composition, temperature and time) is necessary in order to obtain a good reproducibility of the fabrication process. As far as the uniformity
Acknowledgement
This work was supported by the National Research Council of Italy (CNR), within the Nanotechnology initiative, project ‘Lithographic Processes for Nanofabrication’.
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