Introductory Invited Paper
Silicon nanocrystal non-volatile memory for embedded memory scaling

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Abstract

In this paper, we present key features of silicon nanocrystal memory technology. This technology is an attractive candidate for scaling of embedded non-volatile memory (NVM). By replacing a continuous floating gate by electrically isolated silicon nanocrystals embedded in an oxide, this technology mitigates the vulnerability of charge loss through tunnel oxide defects and hence permits tunnel oxide and operating voltage scaling along with accompanied process simplifications. However, going to discrete nanocrystals brings new physical attributes that include the impact of Coulomb blockade or charge confinement, science of formation of nanocrystals of correct size and density and the role of fluctuations, all of which are addressed in this paper using single memory cell and memory array data.

Introduction

The scaling of conventional floating gate Flash memories for embedded applications is becoming increasingly difficult primarily because reliability concerns have limited the bottom or tunnel oxide to a thickness of about 10 nm. This in turn manifests in the high peripheral voltages necessary to operate the memory module making embedding this technology inefficient. From a manufacturing viewpoint, there is process complexity associated with embedding this memory with standard CMOS and manifests as about 10 mask adders. Non-volatile memory technology based on discrete silicon nanocrystals has been shown to be immune to oxide defects which arise during program/erase operations and allows reduction of the tunnel oxide thickness and consequently, memory operating voltage [1], [2], [3]. Fig. 1 shows a schematic cross section of a nanocrystal memory device with a layer of isolated Si nanocrystals forming the floating gate. Typically the nanocrystals may be between 3 and 10 nm in diameter.

The use of silicon nanocrystals as the charge storage medium has significant benefits over that of nitride in SONOS type memories when operating with hot carrier injection (HCI) for programming and Fowler–Nordheim (FN) tunneling for erase due to the ability to utilize tunnel oxide thickness in the order of 5 nm, which are needed to mitigate read disturb effects. At this tunnel oxide thickness, issues that impact SONOS type memories such as erase saturation [4] shown in Fig. 2 are not present in the nanocrystal-based memory. This erase saturation makes SONOS erase less as the erase voltage or the tunnel oxide thickness is increased. The scaling of the tunnel oxide in nanocrystal memories results in embedded memory modules which can operate with a maximum on chip voltage of 6 V allowing reduction of the memory module size by up to a factor of two [2].

However, the replacement of a floating gate by nanocrystals brings new physical aspects and challenges. Charge confinement effects in nanocrystals can influence device operation and characteristics. Further, optimal device performance requires the formation of nanocrystals of the correct size and density and preserving them during subsequent processing. Since the nanocrystals are not formed by patterning, there is stochasticity in their assembly and hence fluctuations can become important. In this paper, we discuss the salient aspects of nanocrystal memory for HCI/FN operation.

The outline of this paper is as follows: in Section 2, we discuss the unique features of nanocrystal memory; in Section 3, we review the bit-cell integration emphasizing the deposition of silicon nanocrystals by CVD and their subsequent passivation; in Section 4, we discuss memory bit-cell data characteristics; in Section 5, we discuss the role of nanocrystal fluctuations and in Section 6, we summarize the paper.

Section snippets

Charge storage in silicon nanocrystals

In this section, we summarize some of the salient aspects of nanocrystal memory devices such as that shown in Fig. 1. The threshold voltage shift due to electron storage is given by [1] asΔVt=npqεoxtcontrol+εoxtnc2εSi,where n is the nanocrystal number density, p is the average number of electrons stored per nanocrystal, q is the electronic charge, ε represents the medium permittivity, tnc is the nanocrystal diameter and tcontrol represents the control oxide thickness. Clearly, for storing a

Nanocrystal engineering

As has been discussed in the previous section, crucial to making a nanocrystal memory is the ability to form nanocrystals at the required densities and size. Numerous efforts have focused on obtaining a high density of nanocrystals through a variety of techniques including aerosol technique, ion implantation, direct chemical vapor deposition (CVD) and recrystallization anneal of amorphous-Si. Direct CVD of silicon is preferred over ion implantation and recrystallization anneal due to the

Memory characteristics

The discrete nature of nanocrystals and the inherent limitations of charge storage due to coulomb blockade manifest themselves in the electrical operation of the NVM bit-cells. For example as described in Section 2 the symmetric fields during erase operation result in an erase saturation threshold voltage that is independent of the applied voltage. In this section we describe some of the memory characteristics of nanocrystal bit-cells that are inherent results of the use of silicon nanocrystals

Effect of fluctuations

As nanocrystals are formed by island growth during CVD, a concern for nanocrystal memories is the impact of nanocrystal fluctuations from device to device. It turns out that the physics of nucleation and growth in CVD can be used to minimize fluctuations. Further, the non-local nature of the influence of a charge located in the nanocrystal mitigates the effect of nanocrystal spatial variations. In this section, we discuss these two ideas.

Nanocrystal nucleation and growth during CVD is not

Summary

In this paper, we have reviewed the salient features of silicon nanocrystal-based non-volatile memory which provides a pathway for tunnel oxide and operating voltage scaling. It is shown that the replacement of a continuous floating gate by a floating gate brings in effects of charge confinement (Coulomb blockade) that influences the optimal nanocrystal size/separation characteristics as well as device properties such as gate disturbance. Data from single bit-cells and 4 Mb arrays show that ±6 V

Acknowledgements

The authors would like to thank R. Puglisi, C. Bongiorno and S. Lombardo of CNR-IMM in Catania, Italy for EFTEM analysis of nanocrystal distribution properties. They would also like to thank Freescale’s Austin Technology and Manufacturing Center for providing support to the project.

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