Nanostructuring Si surface and Si/SiO2 interface using porous-alumina-on-Si template technology. Electrical characterization of Si/SiO2 interface

https://doi.org/10.1016/j.physe.2006.12.008Get rights and content

Abstract

In this work, anodic porous alumina thin films with pores in the nanometer range are grown on silicon by electrochemistry and are used as masking material for the nanopatterning of the silicon substrate. The pore diameter and density are controlled by the electrochemical process. Through the pores of the alumina film chemical oxidation of the silicon substrate is performed, leading to the formation of regular arrays of well-separated stoichiometric silicon dioxide nanodots on silicon, with a density following the alumina pores density and a diameter adjustable by adjusting the chemical oxidation time. The alumina film is dissolved chemically after the SiO2 nanodots growth, revealing the arrays of silicon dioxide dots on silicon. In a next step, the nanodots are also removed, leaving a nanopatterned bare silicon surface with regular arrays of nanopits at the footprint of each nanodot. This silicon surface structuring finds interesting applications in nanoelectronics. One such application is in silicon nanocrystals memories, where the structuring of the oxidized silicon surface leads to the growth of discrete silicon nanocrystals of uniform size. In this work, we examine the electrical quality of the Si/SiO2 interface of a nanostructured oxidized silicon surface fabricated as above and we find that it is appropriate for electronic applications (an interface trap density below 1–3×1010 eV−1 cm−2 is obtained, indicative of the high quality of the thermal silicon oxide).

Introduction

Nanopatterned oxidized silicon surfaces find important applications in nanoelectronics and self-assembly of quantum dots [1], [2], [3], [4]. Conventional techniques used in this respect are (a) electron beam lithography combined with etching and (b) ion beam milling using focused ion beams. Both of these techniques offer accuracy, repeatability and flexibility in the design, but are costly and relatively slow. Alternatively, when periodic structures are needed on silicon, template technology by electrochemistry may be used, which may be applied on large areas, and is consequently very fast and low-cost technique. Anodic alumina thin films on silicon may be used in this respect. These films are fabricated by anodization of aluminum films on a silicon substrate and, under specific electrochemical conditions, they show regular vertical pores distributed in the plane in a hexagonal close-packed (HCP) structure. The size and density of pores is adjustable by changing the electrochemical conditions used [5], [6], [7], [8], [9], [10], [11].

In a previous work [12], [13], the authors developed a technology using very thin anodic porous alumina films on silicon for fabricating two-dimensional arrays of SiO2 quantum dots on silicon by chemical oxidation of the silicon substrate through the pores. The size of the dots depends on the oxidation time and chemical solution used and the dots material is stoichiometric SiO2. Since the dots are grown by consuming silicon from the substrate, the remaining silicon surface if we remove the dots shows the negative pattern of that of the dots-containing surface (arrays of pits on Si following the pore distribution).

In this work, we used capacitance–voltage (C–V) techniques to characterize the Si/SiO2 interface in two cases:

  • (a)

    In samples with the two-dimensional arrays of SiO2 dots fabricated as above and further oxidized at high temperature in order to grow 6-nm-thick thermal silicon oxide in the areas between the dots and at the same time to increase the vertical thickness of the dots.

  • (b)

    In samples as in (a) from which the SiO2 dots were removed and the samples were then oxidized under the same conditions as above so as to fabricate a 6-nm-thick silicon oxide film of homogeneous thickness on all the patterned silicon surface.

From C–V curves on fabricated capacitors, the density of interface states was calculated.

Section snippets

Sample fabrication

The process for sample fabrication is illustrated in more detail in Fig. 1. An Al film, 500-nm thick, was first grown on a p-type silicon wafer by electron gun evaporation. An ohmic contact was formed on the backside of the wafer and the sample was anodized in sulfuric acid aqueous solution, 6% in volume, under a constant voltage of 20 V at room temperature. Under these conditions, a porous alumina thin film was grown on silicon, containing vertical pores ordered on the surface in HCP arrays.

Conclusions

Nanopatterning of a silicon surface was performed by growing two-dimensional arrays of SiO2 dots on silicon through an anodic porous alumina thin film and oxidizing the resulting samples after chemical etching of the alumina film. Two kinds of samples with an undulated Si/SiO2 interface were fabricated. In the first sample, the SiO2 dots were left on the silicon surface, thus an oxide structure of inhomogeneous thickness was grown after oxidation, while in the second case the dots were removed

References (16)

  • Y. Nitta et al.

    Surf Sci.

    (2000)
  • S. Lazarouk et al.

    Microl. Eng.

    (2000)
  • D.H. Kuo et al.

    Thin Sol. Films

    (2001)
  • M. Kokonou et al.

    Mater. Sci. Eng.

    (2003)
  • Y.F. Mei et al.

    Physics Lett A

    (2003)
  • M. Schulz

    Microelectron. Eng.

    (1998)
  • L. Vescan et al.

    Appl. Phys. Lett.

    (2003)
  • E.S. Kim et al.

    Appl. Phys. Lett.

    (1998)
There are more references available in the full text version of this article.

Cited by (0)

View full text
Copyright © 2007 Elsevier B.V. All rights reserved.