A wafer-scale etching technique for high aspect ratio implantable MEMS structures

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Abstract

Microsystem technology is well suited to batch fabricate microelectrode arrays, such as the Utah electrode array (UEA), intended for recording and stimulating neural tissue. Fabrication of the UEA is primarily based on the use of dicing and wet etching to achieve high aspect ratio (15:1) penetrating electrodes. An important step in the array fabrication is the etching of electrodes to produce needle-shape electrodes with sharp tips. Traditional etching processes are performed on a single array, and the etching conditions are not optimized. As a result, the process leads to variable geometries of electrodes within an array. Furthermore, the process is not only time consuming but also labor-intensive. This report presents a wafer-scale etching method for the UEA. The method offers several advantages, such as substantial reduction in the processing time, higher throughput and lower cost. More importantly, the method increases the geometrical uniformity from electrode to electrode within an array (1.5 ± 0.5% non-uniformity), and from array to array within a wafer (2 ± 0.3% non-uniformity). Also, the etching rate of silicon columns, produced by dicing, are studied as a function of temperature, etching time and stirring rate in a nitric acid rich HF–HNO3 solution. These parameters were found to be related to the etching rates over the ranges studied and more importantly affect the uniformity of the etched silicon columns. An optimum etching condition was established to achieve uniform shape electrode arrays on wafer-scale.

Introduction

A major design parameter for neural interfaces is the electrode geometry [1], [2], [3], [4], [5], [6], [7]. The geometrical characteristics of individual electrodes influence many of the electrical properties (impedance, capacitance, etc.) [6]. Thus uniformity of electrode geometry over each array is important. Furthermore, the penetrating electrodes in an implanted array must compromise as little cortical volume as possible (ideally zero). Thus each electrode must be made as slender as possible, and should have sharp tips (<1 μm diameter) and be sufficiently long to be able to reach neurons, yet retain sufficient strength to withstand the implantation procedure. Also, the electrode should have a cylindrical geometry (or slightly conical) so that they induce minimum tissue inflammation [8], [9]. It is desirable to minimize the engineering tolerances (variation in electrode geometry from array to array) so that one can reliably interpret the observed variations in physiological results.

The UEA consists of 100 microelectrodes, which are 1.5 mm in length, supported by a 0.5 mm back plane. Fig. 1 shows a cartoon image of the UEA. The electrodes of the UEA are electrically isolated from each other by a moat of glass that surrounds the base of each electrode [6], [7]. The UEA comes in various configurations such as the slant [10] and the convoluted electrode arrays [11]. An important and early step in the array fabrication is the etching of electrodes to produce needle-shape electrodes with sharp tips. Etching of the UEA has two-steps consisting of (1) dynamic and (2) static etching [6]. Square columns are fabricated by dicing and are subsequently transformed into rounded and pointed electrodes through a wet etching process (mixture of HF (49%)–HNO3 (69%) in a ratio of 1:19 by volume) that rounds the column corners and sharpens the tip. Traditional etching processes are performed on a single array, and the etching conditions are not optimized resulting in variable geometries of electrodes within an array. Furthermore, the process is not only time consuming but also labor-intensive. In order to achieve geometrical uniformity in electrodes, a wafer-scale etching method was developed and optimum etching conditions were investigated in this paper.

The wet etching of silicon with HF–HNO3 mixtures is widely used in the semiconductor industry and in the production of solar cells [12], [13], [14], [15], [16], [17]. This etch process is employed for the removal of work damage or roughness (e.g., caused by sawing of wafers), for the planar removal of silicon, or for texturing of the surface [13]. A detailed study of the etching mechanism was done by Robbins and Schwartz [12], [13], [14], [15] for planar silicon surfaces. In the literature, the etching of silicon in HF–HNO3 mixtures is described as two-step chemical process that includes (1) oxidation of Si to SiO2 by nitric acid (Eq. (1)) and (2) etching of SiO2 by HF (Eq. (2)). The overall reaction is given in Eq. (3).3Si + 4HNO3  3SiO2 + 4NO↑ + 2H2OSiO2 + 6HF  H2SiF6 + 2H2O3Si + 4HNO3 +18HF  3H2SiF6 + 4NO↑ + 8H2O

The crucial step in this reaction is the oxidation of silicon by nitric acid. For isotropic etching involving HF–HNO3, water or acetic acid (etchant popularly known as HNA) are used as diluents to modify the rate of reaction, finish of the etched surface, or to cause preferential etching of certain crystallographic planes [12], [13], [14], [15]. The topography of the etched silicon surface depends on the composition of the etch solution. In the literature, iso-etch curves for various weight percentages of the constituents for an HF–HNO3 system have been reported [15]. The ratio between HF, HNO3 and diluents determines if the etching is diffusion limited or reaction limited. Furthermore, the etch rate is higher in convex corners resulting in the development of rounded corners and edges [15]. If diluent is added, the reaction becomes reaction rate-limited, leading to decrease in etch rate and sharp peaked corners and edges [15]. To make smooth and rounded electrodes it is important to have dissolution step (Eq. (2)) as diffusion limited [12], [13], [14], [15]. Thus this study was limited to nitric acid rich HF (49%)–HNO3 (69%) system in a ratio of 1:19 by volume.

Section snippets

Dicing

A 2-mm thick, 75-mm diameter p-type, c-Si (1 0 0) wafer with a resistivity of 0.01–0.05 Ω cm was used as substrates. A Disco dicing saw, DAD 640, is used to cut two orthogonal sets of deep kerfs into the silicon wafer. Vertical columns were formed in each array by making 13 cuts of 1.5 mm depth with an index of 0.4 mm. The wafer was then rotated by 90° and an additional 13 cuts were made with the same parameters. The thirteen cuts yielded 10 rows of electrodes plus one extra row of electrodes on all

Agitation

Agitation helps in maintaining the concentration of the reactants and the product uniform throughout the solution thereby bringing more reactants to the silicon surface and removing products including nitrous oxide bubbles from the surface. Stirring the acid solution creates an aggressive and continuous flow of the etchant into the dicing kerfs, to generate isotropically etched square columns with rounded corners. Nitrous oxide bubbles trapped between the rectangular silicon columns would

Discussion

Although electrode materials (for example platinum, iridium oxide, conducting polymers etc.) coated on the tips of the electrode affects the electrical properties such as impedance [18], [19], [20], the uniformity in electrical properties is directly influenced by the geometry of the electrodes. Accordingly, the wafer-scale etching technique developed in this work is designed to achieve geometrical uniformity. The optimized etching parameters are listed in Table 1. In order to evaluate the

Conclusion

This paper describes a cost effective, mask-less, wafer-scale method for etching high aspect ratio (15:1) implantable MEMS structures. The technique employs nitric acid rich HF–HNO3 wet etchant (1:19 by volume) to reproducibly achieve uniform shape electrode arrays. The unique combination of etching parameters significantly increases the etching uniformity within an array and across the wafer. The major advantage of this method compared to other techniques employed for etching high aspect ratio

Rajmohan Bhandari received his B.S. and M.S. degrees in physics from Garhwal University, Dehradun, India, in 1996 and 1998. In 2000 he received M.Tech. degree in physics from Indian Institute of Technology (IIT), Delhi, India, with majors in MEMS. He worked in a MEMS foundry in Singapore, as a Product Engineer, from 2001 to 2004. He worked as a Research Assistant in University of Calgary, Canada from 2004 to 2005. From 2006 to 2009 he was a research assistant in the Integrated Neural Interface

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    Rajmohan Bhandari received his B.S. and M.S. degrees in physics from Garhwal University, Dehradun, India, in 1996 and 1998. In 2000 he received M.Tech. degree in physics from Indian Institute of Technology (IIT), Delhi, India, with majors in MEMS. He worked in a MEMS foundry in Singapore, as a Product Engineer, from 2001 to 2004. He worked as a Research Assistant in University of Calgary, Canada from 2004 to 2005. From 2006 to 2009 he was a research assistant in the Integrated Neural Interface Program (INIP) at University of Utah. In 2009 he received PhD in Electrical Engineering from University of Utah. His dissertation was based on wafer-scale fabrication of penetrating neural microelectrode arrays. From 2008 to 2009 he worked as a Consultant in Blackrock Microsystems, Salt Lake City, USA. Since 2009 (till date) he is Senior R&D MEMS/Materials Engineer at Blackrock Microsystems. His research interest includes design, fabrication and testing of implantable microdevices, biocompatible materials, and system integration.

    Sandeep Negi received his B.S. and M.S. degrees in physics from Garhwal University, Dehradun, India, in 1996 and 1998, and his M.Tech. degree in physics from Indian Institute of Technology (IIT), Delhi, India, in 2000. From 2001 to 2004, he worked in CMOS and MEMS industry in Singapore as a product engineer. From 2004 through 2005, he worked as a research assistant in University of Calgary, Calgary, Canada. He received his Ph.D. degree in electrical and computer engineering from University of Utah, Salt Lake City, USA in 2009. In his Ph.D. he worked on the materials and novel processes for effective charge injection at the stimulating electrode/tissue interface for the safe and efficacious neuroprostheses. From 2006 to 2009 he was a research assistant in the Integrated Neural Interface Program (INIP) at University of Utah. Since 2009 till date, he is with Blackrock Microsystems, Salt Lake City, USA, working as a senior MEMS/Materials engineer. His research interest includes the design, fabrication and testing of MEMS and BioMEMS devices and deposition and characterization of thin films.

    Loren Rieth received his B.S. degree in Materials Science from The Johns-Hopkins University, Baltimore, MD, in 1994. He received his Ph.D. in Materials Science and Engineering from the University of Florida, Gainesville, FL, in 2001. From 2001 to 2003, he was a Postdoctoral Research Associate at the University of Utah, Salt Lake City, UT, and continued on at the University of Utah as a Research Assistant Professor in Materials Science (2003–2005), and Electrical and Computer Engineering (2004–present). His research is focused on deposition and characterization of thin film materials for sensors (chemical, physical, and biological), MEMS, BioMEMS, and energy production.

    Florian Solzbacher received his M.Sc. in electrical engineering from the Technical University Berlin in 1997 and his Ph.D. from the Technical University Ilmenau in 2003. He is Director of the Microsystems Laboratory at the University of Utah and a faculty member in the Departments of Electrical and Computer Engineering, Materials Science and Bioengineering; and he is responsible for the Utah branch office of the Fraunhofer IZM, Germany. Dr. Solzbacher is co-founder of First Sensor Technology GmbH, an established supplier to the automotive and process control industry in the USA, Europe and Asia. He is Chairman of the German Association for Sensor Technology AMA. His work focuses on harsh environment microsystems, sensors and materials. He is author of over 60 scientific and engineering publications and book chapters on MEMS devices, technologies and markets for Harsh Environments. Since 2004 he has been Chairman of Sensor + Test, the world's largest international trade fair and ensemble of conferences for sensors, metrology and testing.

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