Elsevier

Solid-State Electronics

Volume 49, Issue 9, September 2005, Pages 1497-1503
Solid-State Electronics

Field effect and Coulomb blockade in silicon on insulator nanostructures fabricated by atomic force microscope

https://doi.org/10.1016/j.sse.2005.07.012Get rights and content

Abstract

The comprehensive understanding of the electrical behaviour of silicon nanostructures becomes more and more important for the evolution of the microelectronics towards nanoelectronics. In this context, we present a complete bench test for the study of silicon nanostructures, from the fabrication by a non-conventional technique, to the electrical characterisation at room and low temperature. Nanostructures with lateral gates are fabricated with an atomic force microscope (AFM) on silicon on insulator (SOI) substrates. At room temperature, we demonstrate a field effect transistor-like behaviour due to the backgate and also to the lateral gate. At low temperature, the electrical transport is a superimposition of the field effect and single-electron phenomena (Coulomb blockade). We demonstrate the one-dimensional character of the electrical transport at low temperature using a theoretical model for arrays of dots.

Introduction

The trend in microelectronics is to reduce the dimension of the devices. In this context, nowadays, there is a real crossing from microelectronics to nanoelectronics and two types of problems are brought up: difficulties of fabricating the structures and understanding the new transport phenomena that may appear in very low-scale devices.

From the fabrication point of view, the limits of optical lithography techniques are more and more obvious, in terms of resolution, flexibility, cost etc., so, new approaches are needed. Atomic Force Microscopy (AFM) based lithography is one of the most promising alternative techniques that emerges. Typically, AFM is used to image the surface of a sample, by scanning a tip onto the surface. The tip may induce changes in the surface in very precise conditions (for example by applying a potential between the tip and the scanned surface), so AFM can become a high resolution lithography tool.

The first description of nanostructures fabrication by AFM lithography on SOI substrates was described by Campbell et al. [1]. The refinements of this method, such as the oxidation in tapping mode [2] or the use of a pulsed tension on the tip [3], have improved the lateral resolution of the structures designed. Later developments of this technique on SOI substrates are presented in Refs. [4], [5].

The scientific groups that are working on silicon nanowires are typically specialised either in the fabrication or in the study of the electrical transport. The main advantage of our work is that we do fabrication by a flexible technique and electrical transport measurements at room and low temperature.

The structures presented in this paper are fabricated using the AFM lithography in contact mode with a pulsed-biased-tip. In order to reveal silicon nanostructures an etching step is necessary. The use of SOI substrates is compulsory because the buried oxide layer acts as an etch stop layer. Moreover, the use of SOI ensures high quality interfaces and reproducible electrical properties of the structures, as demonstrated in this article.

Electrical transport at room temperature shows a field effect due to the backgate. This field effect can be well described by the existing SOI models. A field effect due to the lateral gates is also evidenced.

At low temperature, the conduction through the nanostructures is a superposition of the field effect and of Coulomb blockade phenomenon. A model of the transport through an array of dots allows demonstrating that the nanowires act mainly as uni-dimensional structures at low temperatures.

Section snippets

Fabrication

We have chosen to use the oxidation by AFM in contact mode. The fabrication steps [6] are schematically presented in Fig. 1.

The substrates used are Unibond® SOI [7] samples with an ultra-thinned monocrystalline Si layer down to 15 nm and with a 400 nm buried oxide thickness. The samples are doped with Arsenic and we dispose of two doping levels, 1017 cm−3 and 1019 cm−3. Electrical connections are provided by 80 nm thick pads made of degenerately doped silicon.

The first step is to dip the SOI

Field effect in the silicon nanostructures

The nanostructures fabricated were tested in order to investigate their electrical behaviour at room temperature. The nanowires can be compared to the channel of a field effect transistor. However, as their dimensions—thickness and width—are very small the reproducibility of their electrical properties and their FET behavior is not trivial.

Firstly we are demonstrating that at room temperature and for nanostructures fabricated with the same lithographic parameters lead to similar electrical

Coulomb blockade in silicon nanostructures

The electrical properties of the nanostructures at low temperature were also studied. We want to see if the field effect is still present and if other phenomena are revealed.

In IDRAINVBACKGATE curves (Fig. 7(a)) clear oscillations are superimposed with the field effect. Two measurements were done from low backgate voltage to high backgate voltage and other two the reverse way. The peaks obtained in the four curves are superposed; they represent the Coulomb blockade phenomenon. The origin of

Conclusion

Good theoretical and experimental backgrounds are needed for the future development of nanoelectronic devices. We present here a fabrication method together with the electrical measurements (at room and low temperature) of silicon nanostructures.

The non-conventional fabrication method used is based on AFM lithography of ultra-thin highly doped SOI substrates. The final structures are silicon nanowires with lateral gates. The monocrystallinity and the high quality interfaces of the SOI

Acknowledgements

The authors are grateful D. Fraboulet, D. Mariolle and J. Gautier from LETI/CEA Grenoble for providing the ultra-thin SOI substrates.

References (17)

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